Hello
I am an undergraduate working on building Active noise cancellation code.
I could make good secondary path filter FPGA code (which could generate maximum 7k sampling rate).
However, my second FPGA code (for control filter) can generate maximum only 1.19 kHz. (The control filter FPGA code is attached.)
I need 2kHz sampling rate.
Since I am using memory storage method for matrix calculation, I think i can't use pipelining.
So I tried to increase sampling rate as much as i could by making calculation in parallel.
But as i increase the size of the function through parallelizing, compilation gets interrupted due to too much logics.
The file attached can generates 1.19kHz and uses 98.7% of slice LUTs.
What should i do to increase sampling rate?