Generating two synchrouns digital clocks with python nidaqmx

I am trying to generate two synchronous clock for sensor control (i2s protocol shown in the figure below). The main clock (CK) is at 1024hKz. The other one (WS) is 1024/64hKz but should be changing polarity on the negative edge of the main clock.

I am trying to address it by using counters with Python. here is my code:

cltask = nidaqmx.Task(new_task_name="clki2s")

clk_i2s = "PXI1Slot2/ctr0" #PFI12
clk_ws = "PXI1Slot2/ctr1"#PFI13

frequency_clk_i2s = float(1024000) # 16kHz * 64
frequency_ws_i2s = float(frequency_clk_i2s/64)

delay_ws_i2s = (1/frequency_clk_i2s) / 2


cltask.co_channels.add_co_pulse_chan_freq(
   clk_i2s,
   #name_to_assign_to_channel="",
   units=FrequencyUnits.HZ,
   idle_state=Level.LOW,
   initial_delay=0.0,
   freq=frequency_clk_i2s,
   duty_cycle=0.5
)
cltask.co_channels.add_co_pulse_chan_freq(
   clk_ws,
   # name_to_assign_to_channel="",
   units=FrequencyUnits.HZ,
   idle_state=Level.LOW,
   initial_delay=delay_ws_i2s,
   freq=frequency_ws_i2s,
   duty_cycle=0.5
)
cltask.timing.cfg_implicit_timing(sample_mode=AcquisitionType.CONTINUOUS)

Even  using the delay (delay_ws_i2s) the output are two not-syncronized clocks (I guess there is some initial random jitter somewhere). i.e. WS does NOT change polarity on the negedge.

Do you have any suggestion for this problem? Or potential alternatives?