Hello everyone,
The issue that I have is I couldn't find an efficient way of creating a custom digital signal to feed the counter's gate input. I'll elaborate the problem later but first here are the details of the system that I am using:
*DAQ device: PCIe-6363 (Port 0/line0-7 can be used for buffered operations, Port 1 and Port 2 can be used for unbuffered operations or as PFI lines)
*SW: LabVIEW 17.0
*External 10 MHz clock is connected to PFI4. A 10 KHz continuous pulse is generated using a Counter Output Pulse Tick Task (ctr0) based on the 10 MHz external clock. The 10 KHz pulse will be used as the main clock (MAIN CLK) in the system.
Now let's go back to the description of the issue. Assume one (ctr1 in the VI) of the counters (in total there are four counters) in the DAQ device is being used to count the raising edges of some digital signal available at the input port of the counter. For this task, the "Sample Clock Task.vi" is configured such that the source of sampling (source input of the task) is connected to MAIN CLK (output of the associated counter). Furthermore, a Pause Trigger Property Node is used to pause/resume edge counting task. Attached VI shows the system configuration so far.
Here my question is: If the information of shape and time (with respect to MAIN CLK) of the pause trigger signal are known prior to start of all the tasks in the system, how am I going to generate and implement the pause trigger signal at Pause.DigLvl.Src input?
To clear things up:
Assume, I have a 1-D Boolean array (not necessarily be periodic), whose elements and size are known and going to be used to generate the pause trigger waveform. AT EACH rising edge of the MAIN CLK, if the current element of the Boolean array is TRUE (or FALSE), then the state of the Pause Trigger will be HIGH (or LOW). That waveform should appear at the GATE input of ctr1. Is it possible to achieve this? If yes, what would be most efficient way in terms of using resources? Two counters (out of four) left, for example, it would be better if less number of counters are utilized at the end.
Attempts:
I, first, tried to use Digital Output Write Task, which is sampled with MAIN CLK to write the elements of the Boolean array to one of the output ports. However, GATE input of the counter cannot be set to hardware-timed Digital I/O lines (in this case port 0/line0-7). I can select one of the PFI lines (Port1 and Port2) but now those lines are not available for buffered operation that I am using during Write Task.
Second attempt that I am considering is to use "Change Event Detection" feature to realize the pause trigger waveform from a custom Boolean array. This approach is again based on updating the line Port0/line0 at each clock edge, where any transition from LOW to HIGH can be captured by Change Event Detection. I don't know the details of this feature so any feedback regarding the method and/or other issues would be greatly appreciated.
Thanks for reading.
Best,
CHA