Hi,
I am using a counter NI 9361 with a CRio 9040 and Labview 2017 SP1 f3 - NI RIO 17.6 - NI DAQmx 17.6. I configured the Module in FPGA mode. I based my FPGA code on the example provided with Labview 2017 (NI 9361 Counter Digital Input - FPGA.vi + NI 9361 Edge counting (Host).vi). I slightly modified the configuration of the module in the RT part to run in "Quadrature encoder velocity mode". When I run the VI, the FPGA get stuck in the initialization phase (the first module property node).
I found a fix which enable the code to run : set the NI 9361 in Real-time resources mode, deploy it and run another RT VI which contains DaqMX acquisition of this module (quadrature velocity mode). When I configure the module in FPGA mode and run the RT VI the acquisition worked.
I am not able to run the RT Vi every time that I either restart the CRio or change the FPGA Bitfile.
I can run the VI if I disconnect the CRio or close/reopen the project.
Did anyone had similar behavior ? Is there a configuration required at start up in FPGA Mode ? (I looked all the module properties but I couldn't find anything)
Thank you in advance for your help.