Creating Derived Clocks on a cRIO-9068

I have a cRIO-9068 and I am creating a project that is designed to run entirely on the FPGA. I have a base FPGA clock of 40 MHz. I need to create a series of derived clocks (10Hz, 100Hz, 1000Hz and 10,000Hz) each one to drive the polling of a different type of senor plugged into various input modules. However I cannot get to the point of polling the modules as I am unable to perform the most basic task of setting up and creating the clocks that I need to use. 

When I try to create a derived clock It won't let me create anything below 4.69 MHz (See image): 

Method used: (Chasis -> FPGA Target -> 40 MHz Onboard Clock -> (right click) New FPGA Derrived Clock. 

I tried this method to ensure all the clocks would be synchronized. 

Thanks, 

Mat