I would like to provide a syncronized reset pulse (once every 1.5 seconds) using a 6602 card and generate a continuously repeating analog waveform using a 6723 card. I require these signals to remain synconized (to better than 0.2 ms) for one month in a lab environment.
I generate a 5,000 Hz base clock on the 6602 card. I down-convert this clock using a counter for 10 samples HIGH and 7,490 samples LOW (one tick every 1.5 seconds).
I pipe the 5 kHz signal into the 6723 card over an RTSI cable. I use this clock as an analog sample clock to iterate through a table of 7,500 samples (a continuous non-regenetive waveform) to create an analog signal output. I set a trigger for the table to begin continuous output on the rising edge of the 1.5 second reset pulse.
How can I be assured that after one month of continuous cycling every 1.5 seconds that the analog waveform and reset pulse will still be syncronized? I am relying on the counter on the 6602 card to downconvert the 5 kHz base clock, and the 6723 FIFO buffer outputting at the same 5 kHz base clock, to both output samples perfectly over the span of a month without any form of feedback syncronization (I receive an error that re-triggering is not suported by these cards, so that is not an option). Is there documentation stating that the counters on these cards are infalable at this operating speed?
Thank you for your time.