I have one implicit clock and two sample clocks in a VI code. The top section of the code creates a line of square pulses at a “rate of trigger” (implicit clock), the middle section reads APD pulses from an input channel at a “rate of voltage” (sample clock) and the bottom section creates triangular waves at a “rate of voltage” (from “pattern”, also sample clock). To get all of these processes to terminate correctly and at the same time, I connect “Terminal name with device prefix” – which is associated with the implicit clock, to the “source” of all the sample clocks. (see pictures “Allsourceconneted_1” and 2)
Even though the bottom sample clock has its own frequency (rate of voltage), it still produces triangular waves at a rate of “rate of trigger”, due to, I am assuming, the connection to the implicit clock. If I terminate the connection between “Terminal name with device prefix” and “source” for the bottom sample clock (see picture “disconnectbottom”), then it will produce the correct “rate of voltage”. However, the problem is that this bottom section will continue indefinitely and will never terminate the code, even after the “number of samples” exceeds “data” (see the while loop).
How can I get everything to terminate at the same time, but still have different rates between my implicit clock and my two sample clocks? Why does the bottom sample clock not follow the wired rate of "rate of voltage"?