Hi All,
I'm having some problems implementing a delay for an output signal on FPGA.
Basically I need my code to respond to signals with a delay, but during that delay it should still be able to respond to the next signal with the same delay time. However, right now if the pulse is called with the delay that loop is ignoring the next calls to it.
I've attached a diagram of my signals and desired output to illustrate my problem. I've also included a simplification of my code as vi and png.
I've tried to dynamically change the delay time based on if the pulse loop is active, but that doesn't seem to work (not in attached vi).
I'm now thinking that 'wait' might not be the way to go and that I should implement an array with timestamps. The pulse loop would read the earliest array element and execute the pulse generator when timestamp + delay == current time.
I would appreciate your thoughts on this. Any ways to implement this better?
Thanks a lot in advance!