I've got an interesting problem of a device that flips its state between high/low everytime an event happens (so two events make one complete cycle). I'd like to clock an E series synchronously with it, but looking at the documentation I can't see anyway to tell a PFI input or counter to generate a new clock cycle on both the rising and falling edge. Instead, it just generates a new cycle at half the actual event rate.
I realize I could generate a new clock at approximately the same frequency using the internal timebase, but unfortunately any jitter between the two clocks must be very, very small (<5 ns) for my application to work and the internal time base doesn't have great resolution.
Is there some obvious solution I'm missing ?