Hi all,
I am trying to run a finite pulse train as a master clock for an acquisition application, which should run continuously for a specified number of pulses. In addition, a second pulse train should also run. However, after a certain number of pulses from the first train, the second pulse train should be paused for a set number of pulses, and then resume again.
To test this functionality in Python, I made a simple piece of code that does the following:
- Generate a finite pulse train on CTR0.
- Create a High/Low gating signal on DIO2 based on CTR0 timing.
- Physically wire DIO2 to PFI2.
- Generate a finite pulse train on CTR1, gated by the signal on PFI2.
CTR0 works fine, and the gating signal on DIO2 looks correct. However, when I probe CTR1 output, the gating is never applied. I have tested all PFI lines, even though the documentation suggests they should work. The 5 V signal is also correctly registered by PFI2.
Currently, I’m out of ideas for further debugging, so I’d greatly appreciate any pointers. If there is a simpler way to achieve the same outcome, I’d love to hear about it.
Best,
Device: BNC-2110 connected to PCIe-6323