Does Rising(falling) edge time and high time influence the determine of trigger(or siganal)[PCIE6363]

Hi!

I use a external sample clock to count edge.

But I find something is wrong:I send 400 external TTL-like(periodicity=100ms) sigal as sample clock,but before the sample clock played,the aquisition is over,which means NI is not receiving the sampling clock correctly.

So then I use a normal edge count task to count the Sample clock signal,I find the number is totally wrong(much larger than expcted input number).

Considering my signal is genarated by a DAC(24bit,100KHz) and not standard(more like triangular wave),so I'd like to know Under what conditions does NI count upward or think it is a sample clock

here is part of my 'ugly' sample clock signal.

which you can see:rising time~0.100s,width~0.3s,MAX~2.0V,low~(-0.9V-0.3V)

the total 'ugly' peak send to counter is 2500,but the edge counter counts  more than 467852 peaks

I'd like to konw why and how to solve this?

Thanks!