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How to create fraction of a tick delay in LabVIEW FPGA?

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Hi

 

I am trying to add more resolution to my counter by adding delays between counters . Using feedback nodes the best delay I can get using 40MHz internal clock is 25ns but I want to get delays much finer than this 

Is the below logic works for ns and less than ns delays? 

Below I can use counter to count edges for signal and delayed signal and then I can keep add more AND logics to give more delays . 

Does a logic like this work?

 

ethen99999_1-1653925197571.png

 


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